| 1 | LAP-VLSI-BT-001 | Design Of Low Power and High-Speed Encoder and Decoder Circuits by Re-Evaluating High Speed Design Values | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 2 | LAP-VLSI-BT-002 | Design Of a Two-Bit Magnitude Comparator Based on Pass Transistor, Transmission Gate and Conventional Static CMOS Logic | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 3 | LAP-VLSI-BT-003 | VLSI Implementation of Image Encryption and Decryption Using Reversible Logic Gates | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 4 | LAP-VLSI-BT-004 | Efficiency Analysis of Adder Architectures: A Comparative Study Across Various Bit Lengths | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 5 | LAP-VLSI-BT-005 | Implementation of a 32-bit MAC Unit in ASIC Flow Using Vedic Multiplier and Carry Save Adder | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 6 | LAP-VLSI-BT-006 | A New Exact Reversible Full Adder for High-Speed Arithmetic Applications | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 7 | LAP-VLSI-BT-007 | Design of BIST (Built-In Self-Test) Embedded Master-Slave Communication using SPI Protocol | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 8 | LAP-VLSI-BT-008 | Implementation of Error Correction Techniques in Memory Applications | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 9 | LAP-VLSI-BT-009 | Area Efficient VLSI Architecture for Reversible Radix-2 FFT Algorithm | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 10 | LAP-VLSI-BT-010 | Reliable CRC-Based Error Detection for Finite Field Multipliers in Cryptography Applications | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 11 | LAP-VLSI-BT-011 | Implementation of RNS and LNS Based Arithmetic Units for Cryptography | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 12 | LAP-VLSI-BT-012 | Design and Implementation of Encryption/Decryption Architectures for BFV Homomorphic Encryption Scheme | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 13 | LAP-VLSI-BT-013 | Power Reduction in Domino Logic using Clock Gating in 16nm CMOS Technology | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 14 | LAP-VLSI-BT-014 | Analysis and Comparison of Leakage Power Reduction Techniques for VLSI Design | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 15 | LAP-VLSI-BT-015 | Design of I2C Master Core with AMBA AHB Interface for High Performance Communication | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 16 | LAP-VLSI-BT-016 | Comparative Study of Test Pattern Generation to Reduce Test Application Time | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 17 | LAP-VLSI-BT-017 | Low Power and Area Efficient Address Decoder Design for SRAM | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 18 | LAP-VLSI-BT-018 | Design of Audio/Video CODEC using VLSI Architecture | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 19 | LAP-VLSI-BT-019 | Prototype Design of a Microprocessor using Verilog HDL | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 20 | LAP-VLSI-BT-020 | Performance Analysis of MAC Unit with Various Parallel Adders | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 21 | LAP-VLSI-BT-021 | Synthesis of AMBA APB Bus Protocol | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 22 | LAP-VLSI-BT-022 | Design & Implementation of 32-Bit MIPS Softcore Processor with Enhanced Instruction Set on FPGA | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 23 | LAP-VLSI-BT-023 | Symmetric Ternary Logic System & Its Logic Composition Methodology | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 24 | LAP-VLSI-BT-024 | Design and Analysis of Power Efficient Four-Phase Pipelined ALU | VLSI / Verilog / FPGA | B.Tech | View Abstract |
| 25 | LAP-VLSI-BT-025 | Performance Analysis of ALU with Various Adders & Multipliers for Image Processing | VLSI / Verilog / FPGA | B.Tech | View Abstract |
